Title System-on-chip test architectures : nanometer design for testability / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba

Published Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008

Click on the following:
EBSCO eBooks
ProQuest Ebook Central

Copies

Description 1 online resource (xxxvi, 856 pages) : illustrations Series The Morgan Kaufmann series in systems on silicon Morgan Kaufmann series in systems on silicon. Contents Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends Summary Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students Bibliography Includes bibliographical references and index Notes English Print version record Subject Systems on a chip -- Testing Integrated circuits -- Very large scale integration -- Testing Integrated circuits -- Very large scale integration -- Design TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- VLSI & ULSI. TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Logic. COMPUTERS -- Logic Design. Systems on a chip -- Testing. Integrated circuits -- Very large scale integration -- Testing. Integrated circuits -- Very large scale integration -- Design. Integrated circuits -- Very large scale integration -- Design Integrated circuits -- Very large scale integration -- Testing VLSI Genre/Form dissertations. Academic theses Academic theses. Thèses et écrits académiques. Form Electronic book Author Wang, Laung-Terng. Stroud, Charles E. Touba, Nur A. ISBN 9780123739735 012373973X 9780080556802 0080556809 1281100048 9781281100047 9786611100049 6611100040

  Permalink