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Author Bellido, Manuel J., 1964-

Title Logic-timing Simulation And The Degradation Delay Model
Published Singapore : World Scientific, 2005
Online access available from:
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Description 1 online resource (286 pages)
Contents Prologue; Preface; Contents; 1 Fundamentals of Timing Simulation; 2 Delay Models: Evolution and Trends; 3 Degradation and Inertial Effects; 4 CMOS Inverter Degradation Delay Model; 5 Gate-Level DDM; 6 Logic Level Simulator Design and Implementation; 7 DDM Simulation Results; 8 Accurate Measurement of the Switching Activity; References; Index
Summary This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl
Notes Print version record
Form Electronic book
Author Juan Chico, Jorge.
Valencia, Manuel.
ISBN 1281867098
1860947360 (electronic bk.)
9781860947360 (electronic bk.)