| Description |
xix, 788 pages : illustrations ; 26 cm |
| Contents |
1. Architecture and Machines -- 2. Time, Area, and Instruction Sets -- 3. Data: How Programs Behave -- 4. Pipelined Processor Design -- 5. Cache Memory -- 6. Memory System Design -- 7. Concurrent Processors -- 8. Shared Memory Multiprocessors -- 9. I/O and the Storage Hierarchy -- 10. Processor Studies -- Appendix A DTMR Cache Miss Rates -- Appendix B SPECmark vs. DTMR Cache Performance -- Appendix C Modeling System Effects in Caches -- Appendix D New DRAM Technologies -- Appendix E M/G/1 Queues -- Appendix F Some Details on Bus-Based Protocols |
| Bibliography |
Includes bibliographical references and index |
| Subject |
Computer architecture.
|
|
Microprocessors -- Design and construction.
|
| LC no. |
94041225 |
| ISBN |
0867202041 |
|
