| Description |
1 online resource (116 pages) |
| Series |
Synthesis Lectures on Computer Architecture |
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Synthesis lectures in computer architecture.
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| Contents |
Processor Microarchitecture An Implementation Perspective; Synthesis Lectures on Computer Architecture; ABSTRACT; Keywords; Contents; chapter 1: Introduction; 1.1 CLASSIFICATION OF MICROARCHITECTURES; 1.1.1 Pipelined/Nonpipelined Processors; 1.1.2 In-Order/Out-of-Order Processors; 1.1.3 Scalar/Superscalar Processors; 1.1.4 Vector Processors; 1.1.5 Multicore Processors; 1.1.6 Multithreaded Processors; 1.2 CLASSIFICATION OF MARKET SEGMENTS; 1.3 OVERVIEW OF A PROCESSOR; 1.3.1 Overview of the Pipeline; chapter 2: Caches; 2.1 ADDRESS TRANSLATION; 2.2 CACHE STRUCTURE ORGANIZATION |
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2.2.1 Parallel Tag and Data Array Access2.2.2 Serial Tag and Data Array Access; 2.2.3 Associativity Considerations; 2.3 LOCKUP-FREE CACHES; 2.3.1 Implicitly Addressed MSHRs; 2.3.2 Explicitly Addressed MSHRs; 2.3.3 In-Cache MSHRs; 2.4 MULTIPORTED CACHES; 2.4.1 True Multiported Cache Design; 2.4.2 Array Replication; 2.4.3 Virtual Multiporting; 2.4.4 Multibanking; 2.5 INSTRUCTION CACHES; 2.5.1 Multiported vs. Single Ported; 2.5.2 Lockup Free vs. Blocking; 2.5.3 Other Considerations; chapter 3: The Instruction Fetch Unit; 3.1 INSTRUCTION CACHE; 3.1.1 Trace Cache; 3.2 BRANCH TARGET BUFFER |
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3.3 RETURN ADDRESS STACK3.4 CONDITIONAL BRANCH PREDICTION; 3.4.1 Static Prediction; 3.4.2 Dynamic Prediction; chapter 4: Decode; 4.1 RISC DECODING; 4.2 THE x86 ISA; 4.3 DYNAMIC TRANSLATION; 4.4 HIGH-PERFORMANCE x86 DECODING; 4.4.1 The Instruction Length Decoder; 4.4.2 The Dynamic Translation Unit; chapter 5 Allocation; 5.1 RENAMING THROUGH THE REORDER BUFFER; 5.2 RENAMING THROUGH A RENAME BUFFER; 5.3 MERGED REGISTER FILE; 5.4 REGISTER FILE READ; 5.5 RECOVERY IN CASE OF MISSPECULATION; 5.6 COMPARISON OF THE THREE SCHEMES; chapter 6 The Issue Stage; 6.1 INTRODUCTION; 6.2 IN-ORDER ISSUE LOGIC |
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6.3 OUT-OF-ORDER ISSUE LOGIC6.3.1 Issue Process when Source Operands Are Read before Issue; 6.3.1.1 Issue Queue Allocation.; 6.3.1.2 Instruction Wakeup.; 6.3.1.3 Instruction Selection.; 6.3.1.4 Entry Reclamation.; 6.3.2 Issue Process when Source Operands Are Read after Issue; 6.3.2.1 Read Port Reduction.; 6.3.3 Other Implementations for Out-of-Order Issue; 6.3.3.1 Distributed Issue Queue.; 6.3.3.2 Reservation Stations.; 6.4 ISSUE LOGIC FOR MEMORY OPERATIONS; 6.4.1 Nonspeculative Memory Disambiguation; 6.4.1.1 Case Study 1: Load Ordering and Store Ordering on an AMD K6 Processor |
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6.4.1.2 Case Study 2: Partial Ordering on a MIPS R10000 Processor. 6.4.2 Speculative Memory Disambiguation; 6.4.2.1 Case Study: Alpha 21264.; 6.5 SPECULATIVE WAKEUP OF LOAD CONSUMERS; chapter 7 Execute; 7.1 FUNCTIONAL UNITS; 7.1.1 The Integer Arithmetic and Logical Unit; 7.1.2 Integer Multiplication and Division; 7.1.3 The Address Generation Unit; 7.1.4 The Branch Unit; 7.1.5 The Floating-Point Unit; 7.1.6 The SIMD Unit; 7.2 RESULT BYPASSING; 7.2.1 Bypass in a Small Out-of-Order Machine; 7.2.2 Multilevel Bypass for Wide Out-of-Order Machines; 7.2.3 Bypass for In-Order Machines |
| Summary |
This lecture presents a study of the microarchitecture of contemporary microprocessors. The focus is on implementation aspects, with discussions on their implications in terms of performance, power, and cost of state-of-the-art designs. The lecture starts with an overview of the different types of microprocessors and a review of the microarchitecture of cache memories. Then, it describes the implementation of the fetch unit, where special emphasis is made on the required support for branch prediction. The next section is devoted to instruction decode with special focus on the particular suppor |
| Notes |
7.2.4 Organization of Functional Units |
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Print version record |
| Form |
Electronic book
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| Author |
Latorre, Fernando.
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| ISBN |
1608454533 |
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9781608454532 |
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