| Description |
1 online resource (254 pages) |
| Contents |
Intro -- Preface -- Contents -- Abbreviations -- List of Figures -- List of Tables -- Chapter 1: Introduction -- 1.1 Variability Effects in Analog IC -- 1.2 Work Motivation -- 1.3 Work Purpose -- 1.4 Book Structure -- References -- Chapter 2: Analog IC Sizing Background -- 2.1 Analog IC Sizing -- 2.2 Automatic Analog IC Sizing -- 2.2.1 Knowledge Based -- 2.2.2 Optimization Based -- 2.2.2.1 Optimization Techniques -- Steepest Descent Optimization -- Linear Programming (LP) -- Geometric Programming -- Simulated Annealing -- Stochastic Pattern Search -- Particle Swarm Optimization |
|
Ant Colony Optimization -- Gravitational Search Algorithm -- Genetic Algorithm -- Nondominated Sorting Genetic Algorithm II -- Multi-objective Evolutionary Algorithm Based on Decomposition (MOEA/D) -- 2.2.2.2 Equation-Based Optimization -- 2.2.2.3 Simulation-Based Optimization -- 2.2.2.4 Model-Based Optimization -- 2.3 Circuit Design and Performance Parameters -- 2.3.1 Feasibility Regions -- 2.3.2 Circuit Design and Performance Parameter Space Relation -- 2.3.3 Parametric Yield -- 2.4 Conclusion -- References -- Chapter 3: Yield Estimation Techniques Related Work |
|
3.1 Yield Estimation Techniques -- 3.1.1 Parametric Yield Definition -- 3.1.2 Monte Carlo Analysis for Parametric Yield Estimation -- 3.1.3 Yield Estimation Methodologies -- 3.1.3.1 Monte Carlo or Quasi Monte Carlo Sample Methods -- 3.1.3.2 Monte Carlo Importance Sampling Methods -- 3.1.3.3 Monte Carlo Model-Based Methods -- 3.1.3.4 Non-Monte Carlo Methods -- 3.2 Commercial EDA tools -- 3.3 Conclusion -- References -- Chapter 4: Monte Carlo-Based Yield Estimation: New Methodology -- 4.1 New MC-Based Yield Estimation Methodology: General Description -- 4.2 Clustering Overview |
|
4.2.1 K-Means Clustering Algorithm -- 4.2.2 K-Medoids Clustering Algorithm -- 4.2.3 Fuzzy c-Means Clustering Algorithm -- 4.2.4 Partitional Clustering Parameters -- 4.2.5 Hierarchical Clustering Algorithm -- 4.3 MC-Based Yield Estimation Using Clustering -- 4.3.1 Infeasible Solution Elimination Module -- 4.3.2 K-Means-Based Methodology for Yield Estimation -- 4.3.3 Solving the False POF Problem -- 4.3.4 Projection of Potential Solutions into the Cluster Representative Individual Yield Line -- 4.3.4.1 Cluster Representative Individual Selection -- 4.3.4.2 K-Means Variable Cluster Number Selection |
|
4.3.5 Hierarchical Agglomerative Clustering for MC-Based Yield Estimation -- 4.3.6 Fuzzy c-Means Application for Accurate and Efficient Analog IC Yield Optimization -- 4.3.6.1 First Step: Identify the Feasible Individuals -- 4.3.6.2 Second Step: Clustering of the Feasible Potential Solutions -- 4.3.6.3 Third Step: Selection of the Cluster Representative Individual -- 4.3.6.4 Fourth Step: Assigning Yield Value to the Remaining Individuals in each Cluster -- 4.4 Conclusion -- References -- Chapter 5: AIDA-C Variation-Aware Circuit Synthesis Tool -- 5.1 AIDA-C Analog IC Design Flow |
| Summary |
This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization |
| Notes |
5.1.1 Setup and Monitoring Block Modules |
|
Print version record |
| Subject |
Integrated circuits -- Design and construction.
|
|
Electrical engineering.
|
|
Electronics engineering.
|
|
Circuits & components.
|
|
Technology & Engineering -- Electrical.
|
|
Technology & Engineering -- Electronics -- General.
|
|
Technology & Engineering -- Electronics -- Circuits -- General.
|
|
Integrated circuits -- Design and construction
|
| Form |
Electronic book
|
| Author |
Guilherme, Jorge Manuel Correia
|
|
Horta, Nuno Cavaco Gomes
|
| ISBN |
9783030415365 |
|
3030415368 |
|
