| Description |
1 online resource (xiii, 418 pages) : illustrations (some color) |
| Series |
Lecture notes in computer science ; 11444 |
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LNCS sublibrary. SL 1, Theoretical computer science and general issues |
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Lecture notes in computer science ; 11444.
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LNCS sublibrary. SL 1, Theoretical computer science and general issues.
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| Contents |
[I]. Applications: 1. Fault-tolerant architecture for on-board dual-core synthetic-aperture radar imaging / Helena Cruz, Rui Policarpo Duarte, and Horácio Neto -- 2. Optimizing CNN-based hyperspectral image classification on FPGAs / Shuanglong Liu, Ringo S.W. Chu, Xiwei Wang, and Wayne Luk -- 3. Supporting columnar in-memory formats on FPGA : the hardware design of Fletcher for Apache Arrow / Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, and Zaid Al-Ars -- 4. A novel encoder for TDCs / Günter Knittel -- 5. A resource reduced application-specific FPGA switch / Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, and Takaichi Yoshida -- 6. Software-defined FPGA accelerator design for mobile deep learning applications / Panagiotis G. Mousouliotis and Loukas P. Petrou |
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[II]. Partial reconfiguration and security: 7. Probabilistic performance modelling when using partial reconfiguration to accelerate streaming applications with non-deterministic task scheduling / Bruno da Silva, An Braeken, and Abdellah Touhafi -- 8. Leveraging the partial reconfiguration capability of FPGAs for processor-based fail-operational systems / Tobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp, and Jürgen Becker -- 9. (ReCo)fuse your PRC or lose security : finally reliable reconfiguration-based countermeasures on FPGAs / Kenneth Schmitz, Buse Ustaoglu, Daniel Große, and Rolf Drechsler -- 10. Proof-carrying hardware versus the stealthy malicious LUT hardware Trojan / Qazi Arbab Ahmed, Tobias Wiersema, and Marco Platzner -- 11. Secure local configuration of intellectual property without a trusted third party / Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche, and Jürgen Becker |
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[III]. Image/video processing: 12. HiFlipVX : an open source high-level synthesis FPGA library for image processing / Lester Kalms, Ariel Podlubne, and Diana Göhringer -- 13. Real-time FPGA implementation of connected component labelling for a 4K video stream / Piotr Ciarach, Marcin Kowalczyk, Dominika Przewlocka, and Tomasz Kryjak -- 14. A scalable FPGA-based architecture for depth estimation in SLAM / Konstantinos Boikos and Christos-Savvas Bouganis |
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[IV]. High-level synthesis: 15. Evaluating LULESH kernels on OpenCL FPGA / Zheming Jin and Hal Finkel -- 16. The TaPaSCo open-source toolflow for the automated composition of task-based parallel reconfigurable computing systems / Jens Korinth, Jaco Hofmann, Carsten Heinz, and Andreas Koch -- 17. Graph-based code restructuring targeting HLS for FPGAs / Afonso Canas Ferreira and João M.P. Cardoso |
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[V]. CGRAs and vector processing: 18. UltraSynth : integration of a CGRA into a control engineering environment / Dennis Wolf, Tajas Ruschke, Christian Hochberger, Andreas Engel, and Andreas Koch -- 19. Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories / João Paulo C. de Lima, Paulo C. Santos, Rafael F. de Moura, Marco A.Z. Alves, Antonio C.S. Beck, and Luigi Carro -- 20. Automatic toolflow for VCGRA generation to enable CGRA evaluation for arithmetic algorithms / André Werner, Florian Fricke, Keyvan Shahin, Florian Werner, and Michael Hübner |
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[VI]. Architectures: 21. ReM : a reconfigurable multipotent cell for new distributed reconfigurable architectures / Ludovica Bozzoli and Luca Sterpone -- 22. Update or invalidate : influence of coherence protocols on configurable HW accelerators / Johanna Rohde, Lukas Johannes Jung, and Christian Hochberger |
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[VII]. Design frameworks and methodology: 23. Hybrid prototyping for Manycore design and validation / Leonard Masing, Fabian Lesniak, and Jürgen Becker -- 24. Evaluation of FPGA partitioning schemes for time and space sharing of heterogeneous tasks / Umar Ibrahim Minhas, Roger Woods, and Georgios Karakonstantis |
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[VIII]. Invited talk: 25. Third party CAD tools for FPGA design : a survey of the current landscape / Brent E. Nelson |
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[IX]. Convolutional neural networks: 26. Filter-wise pruning approach to FPGA implementation of fully convolutional network for semantic segmentation / Masayuki Shimoda, Youki Sada, and Hiroki Nakahara -- 27. Exploring data size to run convolutional neural networks in low density FPGAs / Ana Gonçalves, Tiago Peres, and Mário Véstias -- 28. Faster convolutional neural networks in low density FPGAs using block pruning / Tiago Peres, Ana Gonçalves, and Mário Véstias |
| Summary |
This book constitutes the proceedings of the 15th International Symposium on Applied Reconfigurable Computing, ARC 2019, held in Darmstadt, Germany, in April 2019. The 20 full papers and 7 short papers presented in this volume were carefully reviewed and selected from 52 submissions. In addition, the volume contains 1 invited paper. The papers were organized in topical sections named: Applications; partial reconfiguration and security; image/video processing; high-level synthesis; CGRAs and vector processing; architectures; design frameworks and methodology; convolutional neural networks. -- Provided by publisher |
| Notes |
International conference proceedings |
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Includes author index |
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Online resource; title from PDF title page (SpringerLink, viewed April 11, 2019) |
| Subject |
Adaptive computing systems -- Congresses
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Computer architecture -- Congresses
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Adaptive computing systems
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Computer architecture
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| Genre/Form |
proceedings (reports)
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Conference papers and proceedings
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Conference papers and proceedings.
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Actes de congrès.
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| Form |
Electronic book
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| Author |
Hochberger, Christian, editor.
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Nelson, Brent, editor
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Koch, Andreas, editor
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Woods, Roger, 1963- editor.
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Diniz, Pedro C., editor.
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| ISBN |
9783030172275 |
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3030172279 |
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3030172260 |
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9783030172268 |
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9783030172282 |
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3030172287 |
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