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Author Lutsyk, Petro

Title A pipelined multi-core machine with operating system support hardware implementation and correctness proof / Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul
Published Cham : Springer, 2020
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Description 1 online resource (634 p.)
Series LNCS sublibrary, SL1, Theoretical Computer Science and General Issues
Lecture Notes in Computer Science ; 9999
LNCS sublibrary, SL1, Theoretical Computer Science and General Issues
Lecture notes in computer science ; 9999
Contents Intro -- Preface -- Contents -- 1 Introductory Material -- 1.1 So What? -- 1.1.1 The Element of Chance in Multi-Core Programming -- 1.1.2 Standards and Verification in Classical Architecture versus SystemArchitecture -- 1.2 Overview -- 1.3 Basics -- 1.3.1 Sets, Cross Products and Sequences -- 1.3.2 Boolean Operators -- 1.3.3 Binary and Two's Complement Numbers -- 1.3.4 Memory -- 2 On Hierarchical Hardware Design -- 2.1 Syntax -- 2.1.1 Buses -- 2.1.2 I/O Buses -- 2.1.3 Basic Hardware Units -- 2.1.4 Subunit Declarations -- 2.1.5 Composite Hardware Units
2.1.6 Implicit Labels and Types in Hardware Schematics -- 2.1.7 Size Parameters -- 2.1.8 Recursive Constructions -- 2.1.9 Global Naming -- 2.1.10 Paths, Cycles and Depth -- 2.2 Semantics -- 2.2.1 Values of Input Signals -- 2.2.2 Configurations -- 2.2.3 Hardware Computations -- 2.2.4 Circuit Evaluation -- 2.2.5 Values of Buses and Outputs of Units -- 2.2.6 Updating Configurations -- 2.2.7 Streamlining Notation -- 2.3 Modular Reasoning -- 2.3.1 Tracking Paths -- 2.3.2 Evaluating Circuits -- 2.3.3 The Easy Common Case -- 2.3.4 Cycles of Buses Between Units -- 2.3.5 Updating Configurations
2.4 Expressions and Assignments as Syntactic Sugar -- 2.4.1 Syntax -- 2.4.2 Implementation -- 2.4.3 Semantics -- 3 Hardware Library -- 3.1 Circuit Library -- 3.1.1 Basic Circuits -- 3.1.2 Arithmetic Circuits -- 3.1.3 Branch Condition Evaluation Unit -- 3.2 Control Automata -- 3.3 Random Access Memory (RAM) -- 3.3.1 Basic Design -- 3.3.2 Read Only Memory (ROM) -- 3.3.3 R-W-RAM -- 3.3.4 R-RW-RAM -- 3.3.5 Two port ROM -- 3.3.6 bw-R-RW-RAM -- 3.3.7 bw-R-RW-RAM-ROM -- 3.3.8 GPR-RAM -- 3.3.9 SPR-RAM -- 3.3.10 R-RW-SPR RAM -- 3.4 Register Control -- 3.4.1 Set-Clear Flip-Flop -- 3.4.2 Stabilizer Latch
3.5 Control of Tri-State Buses -- 3.5.1 Justifying the Operating Conditions -- 3.5.2 Controlling Tri-State Buses -- 3.5.3 Arbitration -- 3.5.4 Combined Arbiter and Tri-State Bus -- 3.6 Exercises -- 4 Basic Processor Design -- 4.1 MIPS ISA -- 4.1.1 Instruction Tables -- 4.1.2 Configuration and Instruction Fields -- 4.1.3 Instruction Decoding -- 4.1.4 Reading out Data from Register Files -- 4.1.5 Moves -- 4.1.6 ALU-operations -- 4.1.7 Shift Unit Operations -- 4.1.8 Branch and Jump -- 4.1.9 Memory Operations -- 4.1.10 ISA Summary -- 4.1.11 Software Conditions -- 4.2 A Sequential Processor Design
4.2.1 Hardware Configurations and Simulation Relation -- 4.2.2 Memory Embedding -- 4.2.3 Overview of the Hardware -- 4.2.4 Initialization and Instruction Fetch -- 4.2.5 Straight Forward Constructions -- 4.2.6 Data Accesses -- 4.2.7 Absence of Cycles -- 4.3 Repackaging the Induction Step -- 4.3.1 Numbers and Correctness of Circuit Stages -- 4.3.2 Use of Signals for Instruction Execution -- 5 Pipelining -- 5.1 General Concepts -- 5.1.1 ISA, Circuit Stages and Software Conditions -- 5.1.2 Cost Effectiveness of Pipelining -- 5.1.3 Notation -- 5.2 Basic Pipelined Processor -- 5.2.1 Pipeline Registers
Summary This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operation system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical 5 stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter processor interrupts (IPIs) • I/O-interrupt controller and a disk
Notes 5.2.3 Scheduling Functions
Description based upon print version of record
Bibliography Includes bibliographical references
Subject Computers, Pipeline.
Multiprocessors.
Multiprogramming (Electronic computers)
Computers, Pipeline.
Multiprocessors.
Multiprogramming (Electronic computers)
Form Electronic book
Author Oberhauser, Jonas
Paul, Wolfgang J., 1951-
ISBN 3030432424
3030432432
3030432440
9783030432423
9783030432430
9783030432447