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Author NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices (2006 : Sudak, Ukraine)

Title Nanoscaled semiconductor-on-insulator structures and devices / edited by S. Hall, A.N. Nazarov, V.S. Lysenko
Published Dordrecht : Springer, [2007]
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Description 1 online resource (xiii, 369 pages) : illustrations
Series NATO science for peace and security series - B: Physics and biophysics, 1871-465X
NATO Science for Peace and Security series. B, Physics and biophysics.
Contents Note continued: Substrate effect on the output conductance frequency response of SOI MOSFETs / V. Kilchytska / D. Levacq / D. Lederer / G. Pailloncy / J.-P. Raskin / D. Flandre -- Investigation of compressive strain effects induced by STI and ESL / S. Zaouia / S. Cristoloveanu / A.H. Perera -- Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology / A. Nazarov / V. Lysenko / X. Tang / N. Reckinger / V. Bayot -- Variability in nanoscale UTB SOI devices and its impact on circuits and systems / A. Asenov / K. Samsudin -- Electron transport in silicon-on-insulator nanodevices / F. Gamiz / A. Godoy / C. Sampedro -- All quantum simulation of ultrathin SOI MOSFETs / A. Orlikovsky / V. Vyurkov / V. Lukichev / I. Semenikhin / A. Khomyakov -- Resonant tunneling devices on SOI basis / B. Majkusiak -- Mobility modeling in SOI FETs for different substrate orientations and strain conditions / V. Sverdlov / E. Ungersboeck / H. Kosina
Summary The book details many of the key issues associated with the scaling to nano-dimensions of silicon-on-insulator structures. Some papers offer new insight particularly at the device/circuit interface as appropriate for SOI which is fast becoming a mainstream technology. One of the key issues concerns mobility degradation in SOI films less than about 5nm. The advantages of combining scaled SOI devices with high permittivity (k) dielectric indicates that potential solutions are indeed available down to the 22nm node even with 5nm SOI films. A further key issue and potential 'show stopper' for SOI CMOS is highlighted in a number of invited and contributed papers addressing atomistic level effects. Results are presented for Monte Carlo and drift/diffusion modelling together with device compact models and circuit level simulation and this provided for a broad exposure of the problems from intrinsic physics to the circuit level. The scaling to nano-dimensions takes the technology into the realms of quantum effects and a number of papers addressed this aspect from both the technological and physics aspects. The scope of potential applications for quantum dots, quantum wires and nanotubes are considered. The use of semiconductor materials other than Si, on insulator, is featured in some sections of the book. The potential of III/V, Ge and other materials to facilitate continuation down the roadmap is illustrated by a review of the state-of-the-art
Bibliography Includes bibliographical references and author index
Notes Print version record
In Springer e-books
Subject Semiconductors -- Congresses.
Silicon-on-insulator technology -- Congresses.
Nanoelectromechanical systems -- Congresses.
Nanotechnology -- Congresses.
Genre/Form Conference papers and proceedings.
Conference papers and proceedings.
Form Electronic book
Author Hall, Steve, Ph. D.
Nazarov, A. N. (Alexei N.)
Lysenko, V. S. (Vladimir S.)
ISBN 1402063784
1402063792 (paperback)
9781402063794 (paperback)