| Description |
1 online resource (167 pages) |
| Contents |
Intro -- Preface -- Contents -- 1 Introduction -- 1 System-on-Chip to Network-on-Chip: A Paradigm Shift -- 2 NoC-Based Multi-Core Systems with Three-Dimensional (3D) Integration Technology -- 3 Power and Temperature Issues in NoC-Based Multi-CoreSystems -- 4 Testing of NoC-Based Multi-Core Systems -- 5 Issues in Multi-Core Systems Design with Integrated NoC and 3D Technologies -- 6 Application Mapping and TSV Placement: A CombinedApproach -- 7 Swarm Based Optimizer -- 8 Scope and Motivation of the Works -- 9 Summary of This Book -- 10 Conclusion -- References -- 2 Alternative Approaches |
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1 Application Mapping Techniques -- 1.1 Dynamic Application Mapping Techniques -- 2 Static Application Mapping Techniques -- 2.1 Exact Application Mapping Techniques -- 2.2 Search-Based Application Mapping Techniques -- 2.2.1 Deterministic Search-Based Application Mapping Techniques -- 2.2.2 Heuristic Search-Based Application Mapping Techniques -- 2.2.3 Constructive Heuristics Techniques -- 3 Application Mapping Together with TSV Placement for 3D NoC-Based Multi-Core Systems -- 4 Thermal Management Techniques for NoC-Based Multi-Core Systems |
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5 Thermal-Aware Testing of NoC-Based Multi-Core Systems -- 6 Conclusion -- References -- 3 Iterative Application Mapping with TSV Placement Strategy for Design a 3D NoC-Based Multi-Core Systems -- 1 3D NoC-Based Systems and Routing Algorithm -- 2 TSV Placement and Application Mapping Strategy -- 3 Partitioning Algorithm -- 4 Application Mapping onto Mesh-Based 3D NoC Systems -- 4.1 Initial Mapping Phase -- 4.2 Iterative Improvement Phase -- 5 Experimental Results and Analysis -- 5.1 Results on Different TSV Distributions and MappingStrategies -- 5.2 Impact of TSV Position Selection |
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5.3 Dynamic Performance of Different Mapping and TSV Configurations -- 6 Conclusion -- References -- 4 A Constructive Heuristic for Designing a 3D NoC-Based Multi-Core Systems -- 1 Proposed Heuristic for TSV Placement and Application Mapping -- 1.1 Algorithm Philosophy -- 2 Experimental Results and Analysis -- 2.1 Results on Different TSV Distributions and MappingStrategies -- 2.2 Impact of TSV Position Selection -- 2.3 Dynamic Performance of Different Mapping and TSV Configurations -- 3 Conclusion -- References |
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5 A Discrete Particle Swarm Optimization Technique for Designing a 3D NoC-Based Multi-Core Systems -- 1 ILP Formulation for TSV Placement and Application Mapping -- 1.1 Objective Function -- 1.2 Constraints -- 2 PSO Formulation for TSV Placement and Application Mapping -- 2.1 Particle Formulation and Fitness Function -- 2.1.1 Particle Structure -- 2.1.2 Local and Global Best Particle -- 2.1.3 Evolution of the Generation -- 2.1.4 Swap Operator -- 2.1.5 Swap Sequence -- 2.2 Augmentation to the Basic PSO -- 2.2.1 Usage of Better Random Number Generator -- 2.2.2 Inversion Mutation (IM) |
| Summary |
This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems |
| Notes |
2.2.3 Multiple PSO |
| Bibliography |
Includes bibliographical references and index |
| Notes |
Print version record |
| Subject |
Networks on a chip -- Design
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Networks on a chip -- Testing
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Electronic circuits
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Electronics
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Microelectronics
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Microprocessors
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| Form |
Electronic book
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| Author |
Mathew, Jimson
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| ISBN |
9783030313104 |
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3030313107 |
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