| Description |
1 online resource (139 pages) : illustrations, digital, PDF file |
| Series |
Synthesis lectures on digital circuits and systems ; #19 |
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Synthesis lectures on digital circuits and systems (Online) ; #19.
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| Contents |
Introduction -- Semiconductor materials -- NMOS operation -- Linear region -- Saturation region -- Channel modulation -- Subthreshold mode (cutoff) -- PMOS design -- Variability and mismatch -- How do they happen -- Classes of variability -- Random dopant fluctuation -- Line edge roughness -- Variability and mismatch -- Temperature-induced variability/mismatch -- Leakages and I-drives -- CMOS gates -- Ring oscillators and gate chains -- Variability and mismatch in digital systems -- Effect of interconnect -- Ring oscillator switching characteristics -- Digital correlation -- Defining Idtran voltage -- Simulation of statistical and mismatch effects -- Variability and mismatch parameters -- Verifying randomness -- Variability and mismatch in analog systems I -- Current mirrors -- Global variation -- Cascode current mirror -- Wilson current mirror -- Variability and mismatch in analog systems II -- Operational amplifier -- Input pair matching -- Ideal op-amp -- Open-loop gain -- Negative feedback operation -- DC imperfections in op-amps -- Finite gain -- Nonzero output resistance -- Input bias current -- Input offset voltage -- Common mode gain -- Reducing the common mode effect -- Temperature effects -- AC op-amp nonlinearities -- Mismatch issues in SRAM -- Mismatch and variability -- Lifetime-induced variability -- End of life in digital systems -- Hot carrier injection -- Negative bias temperature instability -- Effects on circuits of NBTI: current mirrors -- Effects on circuits of NBTI: op-amps -- Effects on circuits of NBTI: static random access memory -- Mismatch in nonconventional processes -- What is SOI -- Partially depleted SOI -- Fully depleted SOI (FinFET) -- Considerations that affect both FDSOI and PDSOI -- Circuit effects of high-temperature leakage -- Self-heating and dissipation problems within a device -- DC heating from elsewhere on the same chip -- Transient or AC thermal coupling -- Digital circuits in SOI -- Analog circuits in SOI -- Current mirror: Kink region operation -- Operational amplifier -- Operational transconductance amplifier -- Mismatch correction circuits -- Trimming methods -- Laser fuse -- E-fuse circuit -- Sizing the fusing transistor -- E-fuse sense circuit -- Importance of margin -- EPROM/EEPROM -- FeRAM cell design -- Circuits that can be trimmed -- Frequency -- Voltage trim -- Mismatch trimming -- Case study: power IC design for testability -- Noise -- Component and digital circuit noise -- Component/silicon-induced noise -- Thermal noise -- 1/f noise -- Shot noise -- Burst noise -- Physical sources of noise -- Noise simulations -- 1/f noise BSIM modeling -- Thermal noise -- Jitter and noise in digital circuits: circuit effects -- Noise effects in digital systems -- Noise in ring oscillators -- Dynamic logic -- Input protection -- Noise effects in analog systems -- System on a chip -- Noise in an op-amp -- Effect of noise due to two cascaded amplifiers -- LC oscillator -- Static random access memory -- Radiation hardness in static random access memory -- Circuit design to minimize noise effects -- Guard ringing -- Noise suppression through interconnect -- Supply line noise -- Substrate noise reduction -- Reducing component noise -- Circuit effects and noise -- Smart sensors -- Operational amplifiers -- Noise considerations in SOI -- Substrate coupling -- Substrate capacitance/supply capacitance -- Radiation effects -- SOI component noise -- References -- Index -- Author biography |
| Summary |
Component variability, mismatch, and various noise effects are major contributors to design limitations in most modern IC processes. "Mismatch and Noise in Modern IC Processes" examines these related effects and how they affect the building block circuits of modern integrated circuits, from the perspective of a circuit designer. Variability usually refers to a large scale variation that can occur on a wafer to wafer and lot to lot basis, and over long distances on a wafer. This phenomenon is well understood and the effects of variability are included in most integrated circuit design with the use of corner or statistical component models. Mismatch, which is the emphasis of section I of the book, is a local level of variability that leaves the characteristics of adjacent transistors unmatched. This is of particular concern in certain analog and memory systems, but also has an effect on digital logic schemes, where uncertainty is introduced into delay times, which can reduce margins and introduce 'race' conditions. Noise is a dynamic effect that causes a local mismatch or variability that can vary during operation of a circuit, and is considered in section II. Noise can be the result of atomic effects in devices or circuit interactions, and both of these are discussed in terms of analog and digital circuitry |
| Notes |
Title from PDF title page (viewed Apr 8, 2009) |
| Bibliography |
Includes bibliographical references (pages 133-134) and index |
| Subject |
Integrated circuits -- Design and construction.
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Signal processing -- Digital techniques.
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Integrated.
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Integrated circuits -- Design and construction
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Signal processing -- Digital techniques
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| Form |
Electronic book
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| ISBN |
9781598299427 |
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1598299425 |
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9783031797910 |
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3031797914 |
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