| Description |
1 online resource (466 p.) |
| Contents |
Intro -- Preface -- Objective of the Book -- Organization of the Book -- Acknowledgements -- Contents -- About the Author -- Abbreviations -- 1 Binary Number System -- 1.1 Introduction -- 1.2 Binary Number System -- 1.3 Representation of Numbers -- 1.3.1 Signed Magnitude Representation -- 1.3.2 One's Complement Representation -- 1.3.3 Two's Complement Representation -- 1.4 Binary Representation of Real Numbers -- 1.4.1 Fixed Point Data Format -- 1.5 Floating Point Data Format -- 1.6 Signed Number System -- 1.6.1 Binary SD Number System |
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1.6.2 SD Representation to Two's Complement Representation -- 1.7 Conclusion -- 2 Basics of Verilog HDL -- 2.1 Introduction -- 2.2 Verilog Expressions -- 2.2.1 Verilog Operands -- 2.2.2 Verilog Operators -- 2.2.3 Concatenation and Replication -- 2.3 Data Flow Modelling -- 2.4 Behavioural Modelling -- 2.4.1 Initial Statement -- 2.4.2 Always Statement -- 2.4.3 Timing Control -- 2.4.4 Procedural Assignment -- 2.5 Structural Modelling -- 2.5.1 Gate-Level Modelling -- 2.5.2 Hierarchical Modelling -- 2.6 Mixed Modelling -- 2.7 Verilog Function -- 2.8 Verilog Task -- 2.9 File Handling |
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2.9.1 Reading from a Text File -- 2.9.2 Writing into a Text File -- 2.10 Test Bench Writing -- 2.11 Frequently Asked Questions -- 2.12 Conclusion -- 3 Basic Combinational Circuits -- 3.1 Introduction -- 3.2 Addition -- 3.3 Subtraction -- 3.4 Parallel Binary Adder -- 3.5 Controlled Adder/Subtractor -- 3.6 Multiplexers -- 3.7 De-Multiplexers -- 3.8 Decoders -- 3.9 Encoders -- 3.10 Majority Voter Circuit -- 3.11 Data Conversion Between Binary and Gray Code -- 3.12 Conversion Between Binary and BCD Code -- 3.12.1 Binary to BCD Conversion -- 3.12.2 BCD to Binary Conversion |
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3.13 Parity Generators/Checkers -- 3.14 Comparators -- 3.15 Constant Multipliers -- 3.16 Frequently Asked Questions -- 3.17 Conclusion -- 4 Basic Sequential Circuits -- 4.1 Introduction -- 4.2 Different Flip-Flops -- 4.2.1 SR Flip-Flop -- 4.2.2 JK Flip-Flop -- 4.2.3 D Flip-Flop -- 4.2.4 T Flip-Flop -- 4.2.5 Master-Slave D Flip-Flop -- 4.3 Shift Registers -- 4.3.1 Serial In Serial Out -- 4.3.2 Serial In Parallel Out -- 4.3.3 Parallel In Serial Out -- 4.3.4 Parallel In Parallel Out -- 4.4 Sequence Generator -- 4.5 Pseudo Noise Sequence Generator -- 4.6 Synchronous Counter Design |
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4.7 Loadable Counter -- 4.7.1 Loadable Up Counter -- 4.7.2 Loadable Down Counter -- 4.8 Even and Odd Counter -- 4.9 Shift Register Counters -- 4.10 Phase Generation Block -- 4.11 Clock Divider Circuits -- 4.11.1 Clock Division by Power of 2 -- 4.11.2 Clock Division by 3 -- 4.11.3 Clock Division by 6 -- 4.11.4 Programmable Clock Divider Circuit -- 4.12 Frequently Asked Questions -- 4.13 Conclusion -- 5 Memory Design -- 5.1 Introduction -- 5.2 Controlled Register -- 5.3 Read Only Memory -- 5.3.1 Single Port ROM -- 5.3.2 Dual Port ROM (DPROM) -- 5.4 Random Access Memory (RAM) |
| Summary |
The book is designed to serve as a textbook for courses offered to undergraduate and graduate students enrolled in electrical, electronics, and communication engineering. The objective of this book is to help the readers to understand the concepts of digital system design as well as to motivate the students to pursue research in this field. Verilog Hardware Description Language (HDL) is preferred in this book to realize digital architectures. Concepts of Verilog HDL are discussed in a separate chapter and many Verilog codes are given in this book for better understanding. Concepts of system Verilog to realize digital hardware are also discussed in a separate chapter. The book covers basic topics of digital logic design like binary number systems, combinational circuit design, sequential circuit design, and finite state machine (FSM) design. The book also covers some advanced topics on digital arithmetic like design of high-speed adders, multipliers, dividers, square root circuits, and CORDIC block. The readers can learn about FPGA and ASIC implementation steps and issues that arise at the time of implementation. One chapter of the book is dedicated to study the low-power design techniques and another to discuss the concepts of static time analysis (STA) of a digital system. Design and implementation of many digital systems are discussed in detail in a separate chapter. In the last chapter, basics of some advanced FPGA design techniques like partial re-configuration and system on chip (SoC) implementation are discussed. These designs can help the readers to design their architecture. This book can be very helpful to both undergraduate and postgraduate students and researchers |
| Notes |
Description based upon print version of record |
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5.4.1 Single Port RAM (SPRAM) |
| Bibliography |
Includes bibliographical references and index |
| Notes |
Online resource; title from PDF title page (SpringerLink, viewed October 16, 2023) |
| Subject |
Electronic digital computers -- Design and construction -- Data processing.
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Verilog (Computer hardware description language)
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System design.
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Electronic digital computers -- Design and construction -- Data processing
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System design
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Verilog (Computer hardware description language)
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| Form |
Electronic book
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| ISBN |
9783031410857 |
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3031410858 |
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