| Description |
1 online resource (xiv, 175 pages) : illustrations (some color) |
| Contents |
Preface; Contents; 1 Introduction to Network-on-Chip Design; 1.1 The Physical Medium; 1.2 Flow Control; 1.3 Read-Write Transactions; 1.4 Transactions on the Network: The Transport Layer; 1.4.1 Network Interfaces; 1.4.2 The Network: The Physical Layer; 1.5 Putting It All Together; 1.6 Take-Away Points; 2 Link-Level Flow Control and Buffering; 2.1 Elastic Buffers; 2.1.1 Half-Bandwidth Elastic Buffer; 2.1.2 Full-Bandwidth 2-Slot Elastic Buffer; 2.1.3 Alternative Full-Throughput Elastic Buffers; 2.2 Generic FIFO Queues; 2.3 Abstract Flow Control Model; 2.4 Credit-Based Flow Control |
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2.5 Pipelined Data Transfer and the Round-Trip Time2.5.1 Pipelined Links with Ready/Valid Flow Control; Primitive Cases; 2.5.2 Pipelined Links with Elastic Buffers; 2.5.3 Pipelined Links and Credit-Based Flow Control; 2.6 Request-Acknowledge Handshake and Bufferless Flow Control; 2.7 Wide Message Transmission; 2.8 Take-Away Points; 3 Baseline Switching Modules and Routers; 3.1 Multiple Inputs Connecting to One Output; 3.1.1 Credit-Based Flow Control at the Output Link; 3.1.2 Granularity of Buffer Allocation; 3.1.3 Hierarchical Switching |
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3.2 The Reverse Connection: Splitting One Source to ManyReceivers3.3 Multiple Inputs Connecting to Multiple Outputs Using a Reduced Switching Datapath; 3.3.1 Credit-Based Flow Control at the Output Link; 3.3.2 Adding More Switching Elements; 3.4 Multiple Inputs Connecting to Multiple Outputs Using an Unrolled Switching Datapath; 3.5 Head-of-Line Blocking; 3.6 Routers in the Network: Routing Computation; 3.6.1 Lookahead Routing Computation; 3.7 Hierarchical Switching; 3.8 Take-Away Points; 4 Arbitration Logic; 4.1 Fixed Priority Arbitration; 4.1.1 Generation of the Grant Signals |
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4.2 Round-Robin Arbitration4.2.1 Merging Round-Robin Arbitration with Multiplexing; 4.3 Arbiters with 2D Priority State; 4.3.1 Priority Update Policies; 4.4 Take-Away Points; 5 Pipelined Wormhole Routers; 5.1 Review of Single-Cycle Router Organization; 5.1.1 Credit Consume and State Update; 5.1.2 Example of Packet Flow in the Single-Cycle Router; 5.2 The Routing Computation Pipeline Stage; 5.2.1 Idle-Cycle Free Operation of the RC Pipeline Stage; 5.3 The Switch Allocation Pipeline Stage; 5.3.1 Elementary Organization; 5.3.2 Alternative Organization of the SA Pipeline Stage |
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5.3.3 Idle-Cycle Free Operation of the SA Pipeline Stage5.4 Pipelined Routers with RC and SA Pipeline Stages; 5.4.1 Pipelining the Router Only in the Control Path; 5.4.2 Pipelining the Router in the Control and the Datapath; 5.5 Take-Away Points; 6 Virtual-Channel Flow Control and Buffering; 6.1 The Operation of Virtual-Channel Flow Control; 6.2 Virtual-Channel Buffers; 6.3 Buffer Sharing; 6.3.1 The Organization and Operation of a GenericShared Buffer; 6.3.2 Primitive Shared Buffer for VCs: ElastiStore; 6.4 VC Flow Control on Pipelined Links |
| Summary |
This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a |
| Analysis |
engineering |
|
circuits |
|
procesarchitectuur |
|
process architecture |
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elektronica |
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electronics |
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instrumentatie |
|
instrumentation |
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Engineering (General) |
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Techniek (algemeen) |
| Bibliography |
Includes bibliographical references |
| Notes |
Online resource; title from PDF title page (SpringerLink, viewed September 8, 2014) |
| Subject |
Networks on a chip.
|
|
Computer architecture.
|
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TECHNOLOGY & ENGINEERING -- Mechanical.
|
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Computer architecture
|
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Networks on a chip
|
| Form |
Electronic book
|
| Author |
Psarras, Anastasios, author
|
|
Seitanidis, Ioannis, author
|
| ISBN |
9781461443018 |
|
1461443016 |
|
1461443008 |
|
9781461443001 |
|
