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Authors (Last name first) (1-3 of 3)
Taraate, Vaibbhav,
1 2019 Advanced HDL synthesis and SOC prototyping : RTL design using Verilog Taraate, Vaibbhav, author Singapore : Springer, [2019] Rating: Electronic Resources More...
2 2021 ASIC design and synthesis : RTL design using Verilog Taraate, Vaibbhav Rating: Electronic Resources More...
3 2023 Digital design from the VLSI perspective : concepts for VLSI beginners Taraate, Vaibbhav Singapore : Springer, [2023] Rating: Electronic Resources
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Advanced HDL synthesis and SOC prototyping : RTL design using Verilog