| Description |
1 online resource (681 pages) |
| Contents |
Cover; Half Title; Title Page; Copyright Page; Dedication; Table of Contents; Foreword; Preface; Acknowledgments; Author; PART I Conventional Silicon Based NVM Devices; Chapter 1 Silicon Based Digital Volatile and Nonvolatile Memories: An Introductory Overview; 1.1 Digital Memories and Binary States: Basic Concepts; 1.2 Volatile Memories and NVMs; 1.2.1 Static Random Access Memory: SRAM; 1.2.2 Dynamic Random Access Memory: DRAM; 1.2.3 Read-Only Memory: ROM; 1.2.4 EPROM, EEPROM, and E2PROM; 1.2.5 Recent NVMs: NROM and NAND Flash Memories; 1.3 Memory Hierarchy in Digital Systems |
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1.4 Fundamental Memory Concept in NVMs1.5 NVM Device Groupings and Nomenclature; References; Chapter 2 Historical Progression of NVM Devices; 2.1 Floating-Gate Devices; 2.1.1 The FAMOS Device; 2.1.2 The SAMOS Device; 2.1.3 The SAMOS 8 Kb EAROM; 2.1.4 The SIMOS Device; 2.1.5 Chronology of Floating-Gate Device Evolution; 2.1.6 The HIMOS Cell; 2.1.7 The ETOX/FLOTOX Cell; 2.1.8 The DINOR Cell; 2.1.9 The NAND Cell; 2.2 Conventional Charge-Trapping Devices; 2.2.1 MNOS/MXOS/MONOS/SNOS/SONOS; 2.2.2 Historical Evolution of MNOS, MXOS to SONOS CT Devices; 2.2.3 Evolution of CT-NVM Cell Designs |
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2.2.3.1 Tri-Gate Memory Cell2.2.3.2 Pass Gate Memory Cell; 2.3 Nanocrystal Charge-Trapping NVM Devices; 2.3.1 Early History; 2.3.2 Nanocrystal Physics and Charge Trapping; 2.3.3 Review of Nanocrystal NVM Devices; 2.3.4 Nanocrystal Device General Characteristics; 2.3.5 Silicon Nanocrystal Device Characteristics; 2.3.6 Metal Nanocrystal Device Characteristics; 2.3.7 Germanium Nanocrystal Device Characteristics; 2.4 Direct Tunnel Memory; References; Chapter 3 General Properties of Dielectrics and Interfaces for NVM Devices; 3.0 The NVM Gate Stack Layers and Interfaces |
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3.1 Attributes of Gate Stacks for NVM Devices3.1.1 The Energy Band of the Gate Stack Layers; 3.2 General Properties of Thin Dielectric Films; 3.2.1 Physical, Chemical, and Thermal Stability; 3.2.2 Electronic Properties; 3.2.3 Bulk and Interface Defects and Charge Trapping; 3.2.4 Charge Transport; 3.2.5 Figure of Merit for Selected Metal-Oxide Dielectric Films; 3.2.5.1 Metal Work Function and Electron Affinity; 3.3 Interfaces, Electrode Compatibility, and Process Sensitivity; 3.4 Gate Material for NVM Devices; 3.5 Dielectric Conductivity Mechanisms |
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3.5.1 Bulk-Controlled Poole-Frenfel Mechanism3.5.2 Electrode-Controlled Quantum Mechanical Tunneling Mechanisms; 3.5.3 Direct Tunneling and/or Modified Fowler-Nordheim Tunneling; 3.5.3.1 Fowler-Nordheim Tunneling; 3.5.3.2 Enhanced Fowler-Nordheim Tunneling; 3.6 Carrier Transport Mechanisms for Multilayer Dielectrics; References; Chapter 4 Dielectric Films for NVM Devices; 4.0 Conventional Dielectric Films for NVM Devices; 4.1 Thermal Oxide: SiO2; 4.1.1 Defect Generation and Oxide Degradation; 4.1.1.1 Oxide Reliability; 4.2 CVD or LPCVD Nitride: Si3N4 |
| Summary |
"The primary focus of this book is on basic device concepts, memory cell design, and process technology integration. The first part provides in-depth coverage of conventional nonvolatile memory devices, stack structures from device physics, historical perspectives, and identifies limitations of conventional devices. The second part reviews advances made in reducing and/or eliminating existing limitations of NVM device parameters from the standpoint of device scalability, application extendibility, and reliability. The final part proposes multiple options of silicon based unified (nonvolatile) memory cell concepts and stack designs (SUMs). The book provides Industrial R & D personnel with the knowledge to drive the future memory technology with the established silicon FET-based establishments of their own. It explores application potentials of memory in areas such as robotics, avionics, health-industry, space vehicles, space sciences, bio-imaging, genetics etc."--Provided by publisher |
| Notes |
4.2.1 Nitride Traps, Trap Creation: Process and Stress Sensitivity |
| Bibliography |
Includes bibliographical references and index |
| Notes |
Dr. Arup Bhattacharyya has forty years of leadership and pioneering contributions in the area of microelectronics and nanoelectronics. He has contributed pioneering activities and innovations in process, device, interconnect, and integration of many generations of microelectronics and nano-electronics. His inventions include nearly 300 U.S. and international Patents and invention publications in technologies such as CCD, BIPOLAR, FET, NVM, FLASH, ANTIFUSE, SOI, BICMOS, SOLAR-CELLS, and SOC. Some of the applications of Dr. Bhattacharyya's inventions include electronic Memories, Microprocessors and Controllers, Random and Programmable Logic Devices, Nonvolatile Devices, Energy-conversion devices, ASICs, ASDs, and SMART Electronic Devices. He has experience in R&D leadership, Program management and Technology transfer, Technical Education and Consultancy, Strategic Planning, Infrastructure Development, Product Development, and Manufacturability. Additional experiences include University teaching, volunteering for science and engineering promotion, service to professional organizations, and consultancy to the UN |
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Print version record |
| Subject |
Semiconductor storage devices -- Design and construction
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.
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TECHNOLOGY & ENGINEERING -- Electronics -- Microelectronics.
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TECHNOLOGY / Electricity
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TECHNOLOGY / Electronics / General
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TECHNOLOGY / Electronics / Circuits / General
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Semiconductor storage devices -- Design and construction
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| Genre/Form |
handbooks.
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Handbooks and manuals.
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Guides et manuels.
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| Form |
Electronic book
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| ISBN |
9781351798310 |
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1351798316 |
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9781315206868 |
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1315206862 |
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9781351798327 |
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1351798324 |
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9781351798303 |
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1351798308 |
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