| Description |
xxxi, 526 pages : illustrations ; 24 cm |
| Series |
PC system architecture series |
|
PC system architecture series.
|
| Contents |
Ch. 1. System Overview -- Ch. 2. Processor Overview -- Ch. 3. Processor Power-On Configuration -- Ch. 4. Processor Startup -- Ch. 5. The Fetch, Decode, Execute Engine -- Ch. 6. Rules of Conduct -- Ch. 7. The Processor Caches -- Ch. 8. Bus Electrical Characteristics -- Ch. 9. Bus Basics -- Ch. 10. Obtaining Bus Ownership -- Ch. 11. The Request and Error Phases -- Ch. 12. The Snoop Phase -- Ch. 13. The Response and Data Phases -- Ch. 14. Transaction Deferral -- Ch. 15. IO Transactions -- Ch. 16. Central Agent Transactions -- Ch. 17. Other Signals -- Ch. 18. Instruction Set Enhancements -- Ch. 19. Register Set Enhancements -- Ch. 20. Paging Enhancements -- Ch. 21. Interrupt Enhancements -- Ch. 22. Machine Check Architecture -- Ch. 23. Performance Monitoring and Timestamp -- Ch. 24. MMX: Matrix Math Extensions -- Ch. 25. 450GX and KX Chipsets -- Ch. 26. 440FX Chipset -- Appendix. The MTRR Registers |
| Summary |
Pentium Pro Processor System Architecture describes the hardware and software characteristics of the Pentium Pro processor, the bus protocol it uses to communicate with the system, and the overall machine architecture. Written for computer hardware and software engineers, this book details the internal architecture of the processor, providing insight into how it translates legacy x86 code into RISC instructions, executes them out-of-order, and then reassembles the result to match the original program flow. In detailing the processor's internal operations, the book reveals why the processor generates various transaction types, and how it watches bus traffic generated by other entities to ensure cache consistency |
| Notes |
Includes index |
| Subject |
Pentium (Microprocessor)
|
| Author |
Shanley, Tom.
|
|
MindShare, Inc.
|
| LC no. |
96049786 |
| ISBN |
0201479532 |
|
