| Description |
1 online resource (242 pages) |
| Series |
Research at NaMLab Ser. ; v. 2 |
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Research at NaMLab Ser
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| Contents |
Intro; 1 Introduction; 2 Fundamentals of Leakage Currents in MOSFET Devices; 2.1 Leakage through Gate Oxide; 2.1.1 Thermally Activated Gate Leakage; 2.1.2 Tunneling Leakage Through the Gate Dielectric; 2.2 Subthreshold Leakage from Source to Drain; 2.3 Leakage from Silicon Space Charge Regions to Transistor Bulk; 2.3.1 Leakage Current Mechanisms; 2.3.2 Perimeter Leakage from Source/Drain to Bulk; 2.3.3 Generation Leakage from Channel Region to Bulk; 3 Methodology; 3.1 Current Voltage Measurement; 3.1.1 Basic Current Voltage Characteristics; 3.1.2 Separation of Leakage Pathâ#x80;#x99;s |
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3.1.3 Gated Diode Measurement3.2 Capacitance Voltage Measurement; 3.3 Charge Pumping Measurement; 3.4 Simulation; 3.4.1 Spice Simulation; 3.4.2 TCAD Simulation; 4 Impact of Implant Variations on PFET Leakage Current; 4.1 Process Flow; 4.2 TCAD Simulation of the Process; 4.3 Interface Traps; 4.4 Electrical Measurement and Simulation of Leakage Current; 4.4.1 Source/Drain Leakage; 4.4.2 Source/Drain Extension Leakage; 4.4.3 Generation Leakage from Channel Region to Bulk; 4.4.4 Gate Induced Drain Leakage; 4.4.5 Verification of the Defect Model: Gated Diode Measurement; 4.4.6 Gate Leakage |
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4.4.7 Subthreshold Leakage4.4.8 Conclusion; 4.5 Carbon Implantation into Junction Extension; 4.5.1 Description of Experiment; 4.5.2 Electrical Characterization of Transistor Performance; 4.5.3 Interface Traps; 4.5.4 Carbon Dose Dependent Leakage Current; 4.5.5 Conclusion; 4.6 Arsenic and Phosphorus Implantation for Threshold Voltage Control; 4.6.1 Description of Experiment; 4.6.2 Electrical Characterization of Transistor Performance; 4.6.3 Leakage Current Dependent on Halo- and Vth Implant; 4.6.4 Conclusion; 5 Impact of High-k Process Adjustment on Transistor Leakage Current |
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5.1 High-k Process Flow5.2 TCAD Simulation of the Process; 5.3 Interface Traps; 5.4 Electrical Measurement and Simulation of Leakage Current; 5.4.1 Source/Drain Leakage; 5.4.2 Source/Drain Extension Leakage; 5.4.3 Generation Leakage from Channel Region to Bulk; 5.4.4 Gate Induced Drain Leakage; 5.4.5 Gate Leakage; 5.4.6 Subthreshold Leakage; 5.4.7 Conclusion; 5.5 Comparison of Silicon Oxide and Silicon Nitride Extension Spacer; 5.5.1 Description of Experiment; 5.5.2 Electrical Characterization of Transistor Performance; 5.5.3 Leakage Current Dependence on the Spacer Dielectric |
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5.5.4 Conclusion5.6 Germanium Implantation during Gate Patterning; 5.6.1 Description of Experiment; 5.6.2 Electrical Characterization of Transistor Performance; 5.6.3 Leakage Current Dependence on the Gate Patterning Process; 5.6.4 Conclusion; 6 Summary and Outlook; 6.1 Leakage Currents and Defect Distribution; 6.2 Carbon in the Junction Extension; 6.3 Vth- and Halo Implant; 6.4 Silicon Oxynitride vs. Hafnium Silicon Oxide Gate Dielectric; 6.4.1 Silicon Oxide vs. Silicon Nitride Extension Spacer; 6.4.2 Germanium Implantation for Gate Patterning; 6.5 Outlook; 7 Bibliography |
| Summary |
Annotation The continuous improvement in semiconductor technology requires field effect transistor scaling while maintaining acceptable leakage currents. This study analyzes the effect of scaling on the leakage current and defect distribution in peripheral DRAM transistors. The influence of important process changes, such as the high-k gate patterning and encapsulation as well as carbon co-implants in the source/drain junction are investigated by advanced electrical measurements and TCAD simulation. A complete model for the trap assisted leakage currents in the silicon bulk of the transistors is presented |
| Notes |
8 Personal Bibliography |
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Print version record |
| Subject |
Metal oxide semiconductor field-effect transistors.
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Metal oxide semiconductor field-effect transistors.
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| Form |
Electronic book
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| ISBN |
9783832596668 |
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3832596666 |
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3832532617 |
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9783832532611 |
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