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An architectural leakage power reduction method for instruction cache in ultra deep submicron microprocessors / / Chengyi Zhang, Hongwei Zhou, Minxuan Zhang and Zuocheng Xing --
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2006
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1
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Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals / / Nupur Navlakha, Lokesh Garg, Dharmendar Boolchandani, Vineet Sahula --
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2013
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1
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Architectural Materials from the Pantanello Sanctuary / / Nicoletta Petrillo --43.
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2018
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1
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An Architectural Model for Autonomous Normative Agents / / Baldoino F. dos Santos Neto, Viviane Torres da Silva and Carlos J.P. de Lucena
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2012
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1
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Architectural Model for Generating User Interfaces Based on Class Metadata / / Luiz Azevedo, Clovis Torres Fernandes, Eduardo Martins Guerra
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2013
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1
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