Limit search to available items
Book Cover
Book
Author Liu, Xiao (Senior test engineer), author

Title Trace-Based Post-Silicon Validation for VLSI Circuits / Xiao Liu, Qiang Xu
Published Cham Springer, [2014]

Copies

Location Call no. Vol. Availability
 WATERFT ART&ARCH  621.395 Liu/Tbp  AVAILABLE
Description xv, 108 pages : illustrations (black and white, and colour) ; 25 cm
Series Lecture Notes in Electrical Engineering, 1876-1100 ; Volume 252
Lecture notes in electrical engineering. 1876-1100 ; Volume 252
Contents Contents note continued: 4.3.1.Supporting DfD Hardware for Multiplexed Signal Tracing -- 4.3.2.Signal Grouping Algorithm -- 4.4.Experimental Results -- 4.4.1.Experiment Setup -- 4.4.2.Experimental Results -- 4.5.Conclusion -- 5.Tracing for Electrical Error -- 5.1.Preliminaries and Summary of Contributions -- 5.2.Observing Speedpath-Related Electrical Errors -- 5.2.1.Speedpath-Related Electrical Error Model -- 5.2.2.Speedpath-Related Electrical Error Detection Quality -- 5.3.Trace Signal Selection -- 5.3.1.Relation Cube Extraction -- 5.3.2.Signal Selection for Non-Zero-Probability Error Detection -- 5.3.3.Trace Signal Selection for Error Detection Quality Enhancement -- 5.4.Trace Data Qualification -- 5.5.Experimental Results -- 5.6.Conclusion -- 6.Reusing Test Access Mechanisms -- 6.1.Preliminaries and Summary of Contributions -- 6.1.1.SoC Test Architectures -- 6.1.2.SoC Post-Silicon Validation Architectures -- 6.1.3.Summary of Contributions --
Contents note continued: 6.2.Overview of the Proposed Debug Data Transfer Framework -- 6.3.Proposed DfD Structures -- 6.3.1.Modified Wrapper Design -- 6.3.2.Trace Buffer Interface Design -- 6.4.Sharing TAM for Multi-Core Debug Data Transfer -- 6.4.1.Core Masking for TestRail Architecture -- 6.4.2.Channel Split -- 6.5.Experimental Results -- 6.6.Conclusion -- 7.Interconnection Fabric for Flexible Tracing -- 7.1.Preliminaries and Summary of Contributions -- 7.2.Proposed Interconnection Fabric Design -- 7.2.1.Multiplexer Network for Mutually-Exclusive Signals -- 7.2.2.Non-Blocking Concentration Network for Concurrently-Accessible Signals -- 7.3.Experimental Results -- 7.4.Conclusion -- 8.Interconnection Fabric for Systematic Tracing -- 8.1.Preliminaries and Summary of Contributions -- 8.2.Proposed Trace Interconnection Fabric -- 8.3.Proposed Error Evidence Localization Methodology -- 8.4.Experimental Results -- 8.4.1.Experimental Setup -- 8.4.2.Results and Discussion --
Contents note continued: 8.5.Conclusion -- 9.Conclusion
Machine generated contents note: 1.Introduction -- 1.1.VLSI Design Trends and Validation Challenges -- 1.2.Key Contributions and Book Outline -- 2.State of the Art on Post-Silicon Validation -- 2.1.Trace Signal Selection -- 2.2.Interconnection Fabric Design for Trace Data Transfer -- 2.3.Trace Data Compression -- 2.4.Trace-Based Debug Control -- 3.Signal Selection for Visibility Enhancement -- 3.1.Preliminaries and Summary of Contributions -- 3.2.Restorability Formulation -- 3.2.1.Terminologies -- 3.2.2.Gate-Level Restorabilities -- 3.3.Trace Signal Selection -- 3.3.1.Circuit Level Visibility Calculation -- 3.3.2.Trace Signal Selection Methodology -- 3.3.3.Trace Signal Selection Enhancements -- 3.4.Experimental Results -- 3.4.1.Experiment Setup -- 3.4.2.Experimental Results -- 3.5.Conclusion -- 4.Multiplexed Tracing for Design Error -- 4.1.Preliminaries and Summary of Contributions -- 4.2.Design Error Visibility Metric -- 4.3.Proposed Methodology --
Notes "This book includes, but is not limited to, the research work on post-silicon validation during the author Xiao Liu's Ph.D. study"--Preface
Bibliography Includes bibliographical references and index
Notes Also published electronically
Subject Integrated circuits -- Verification.
Integrated circuits -- Very large scale integration -- Design and construction.
Author Xu, Jiang, author
LC no. 2013938757
ISBN 3319005324 (cased)
9783319005324 (cased)
(eBook)
(eBook)