| Description |
1 online resource (173 pages) |
| Contents |
Introduction -- SoC Physical Design Flow and Algorithms -- Physical Design Floor Plan and Placement -- Clock, Reset, and HFN -- Physical Design Routing -- Physical Design Verification |
| Summary |
SoC Physical Design is a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC). The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles. Provides a comprehensive overview of the skills required for complex SoC design and development; Examines SOC design challenges in nanotechnology scales; Offers readers professional tricks to using tools for optimal design runs |
| Bibliography |
Includes bibliographical references and index |
| Notes |
Online resource; title from PDF title page (SpringerLink, viewed June 20, 2022) |
| Subject |
Systems on a chip.
|
|
Systems on a chip
|
| Form |
Electronic book
|
| Author |
Koteshwar, Shivananda R
|
| ISBN |
9783030981129 |
|
3030981126 |
|
