| Description |
1 online resource (418 pages) |
| Series |
River Publishers Series in Electronic Materials and Devices |
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River Publishers series in electronic materials and devices.
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| Contents |
Preface xiii -- Acknowledgements xv -- List of Contributors xvii -- List of Figures xix -- List of Tables xxxvii -- List of Abbreviations xxxix -- 1 Space Radiation Effects in Electronics 1 Luigi Dilillo, Alexandre Bosser, Arto Javanainen and Ari Virtanen 1.1 Space Radiation Environment 2 -- 1.1.1 The Sun 2 -- 1.1.2 The Sunspot Cycle 2 -- 1.1.3 Solar Flares and Coronal Mass Ejections 3 -- 1.1.4 Trapped Particles -- Van Allen Belts 4 -- 1.1.5 South Atlantic Anomaly 5 -- 1.1.6 Galactic Cosmic Rays 6 -- 1.1.7 Space Weather 7 -- 1.1.8 Atmospheric and Ground-Level Radiation Environments 8 -- 1.1.9 Cosmic Rays 9 -- 1.1.10 Radionuclides in the Soil 10 -- 1.1.11 Thermal Neutrons 11 -- 1.1.12 Artificial Radiation Sources 12 -- 1.2 Radiation Effect in Materials and Devices 12 -- 1.2.1 Energetic Charged Particles and Matter 12 -- 1.2.2 Stopping Nomenclature 14 -- 1.2.3 General Theory for Electronic Stopping 14 -- 1.2.4 Stopping Theories and Semi-Empirical Models 15 -- 1.2.5 Nuclear Stopping Force 16 -- 1.2.6 Ion-induced Nuclear Reactions 17 -- 1.3 Radiation Effects in Semiconductors 18 -- 1.3.1 Generation of Electron-Hole Pairs 18 -- 1.3.2 Nuclear Reactions 19 -- 1.3.3 Linear Energy Transfer vs. Electronic Stopping Force 21 -- 1.3.4 Spatially Restricted LET 22 -- 1.3.5 Energy Loss Straggling 23 -- 1.3.6 Applicability of LET 25 -- 1.3.7 Prediction Tools for Stopping Force 26 -- 1.3.8 Cumulative Effect: Total Ionizing Dose and Displacement Damage 28 -- 1.3.9 Single Event Effects 28 -- 1.3.10 Soft Errors 29 -- 1.3.11 Hard Errors 30 -- 1.4 Effect of Radiation on Memory Devices 31 -- 1.4.1 Structure of a Memory 31 -- 1.4.2 Classification and Fault Mechanisms in Memories 35 -- 1.4.3 Memory Accelerated Tests 38 -- 1.4.4 Test Methods 39 -- 1.4.5 Static Mode Testing 40 -- 1.4.6 Dynamic Mode Testing 41 -- 1.5 Radiation Hardness Assurance Testing 43 -- 1.5.1 Beam Requirements 46 -- 1.5.2 TID Tests 47 -- 1.5.3 TNID Tests 48 -- 1.5.4 SEE Tests 48 -- 1.5.5 Sample Preparation 48 -- 1.5.6 TID Tests 48 |
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1.5.7 SEE Tests 49 -- 1.5.8 Radiation Facilities 49 -- 1.5.9 ESA European Component Irradiation Facilities (ECIF) 49 -- 1.5.10 Other Outstanding European Facilities 50 -- 1.5.11 Other Outstanding Facilities in the World 51 -- 1.5.12 Accelerated Test for Memories 51 -- 1.5.13 Memory Test Setup 52 -- 1.5.14 Notes on Test Result Analysis 54 -- 1.6 Conclusion 55 -- References 56 -- 2 RHBD Techniques for Memories 65 Cristiano Calligaro 2.1 Effect of HEPs on Semiconductor Devices 65 -- 2.2 Cumulative Effect: TID 68 -- 2.3 Single Event Latch-up: SEL 74 -- 2.4 Single Event Upset: SEU 76 -- 2.5 From SET to SEU/SEFI/MBU: When a Disturbance Becomes an Error 79 -- 2.6 Radiation Hardening By Design (RHBD) 83 -- 2.7 RHBD at Architectural Level 87 -- 2.8 RHBD at Circuit Level 91 -- 2.9 RHBD at Layout Level 95 -- 2.10 Conclusion 100 -- References 101 -- 3 Rad-hard SRAMs 103 Cristiano Calligaro 3.1 SRAM Foundations: Single Port and Multiple Port 103 -- 3.2 Synchronous or Asynchronous? 118 -- 3.3 SRAM Architectures 124 -- 3.4 Embedded SRAMs 132 -- 3.5 SRAMs' Building Blocks ... Rad-hard of Course 136 -- 3.5.1 Input Buffers and ATDs 136 -- 3.5.2 DEMUXs 139 -- 3.5.3 Sensing 140 -- 3.6 ECC Foundations: The Hamming Code 143 -- References 149 -- 4 One-Time Programmable Memories for Harsh Environments 151 Umberto Gatti 4.1 Introduction 151 -- 4.1.1 NVM Technology Overview 152 -- 4.1.2 OTP Application in Harsh Environments 154 -- 4.2 OTP Memories for Standard CMOS Technologies 157 -- 4.2.1 Principle of Operation 158 -- 4.2.2 CMOS OTP Based on Anti-Fuse 161 -- 4.2.3 Characteristics and Limits 166 -- 4.3 Rad-hard CMOS OTP 169 -- 4.3.1 Critical Features 169 -- 4.3.2 State of the Art 174 -- 4.3.3 RHBD Mitigation: Architectures and Layout 176 -- 4.4 Conclusion 186 -- References 186 -- 5 Rad-hard Flash Memories 191 Anna Arbat Casas 5.1 Introduction 191 -- 5.1.1 Non-volatile Memories Overview 192 -- 5.1.2 Flash NVM: Principle of Operation 194 -- 5.1.3 Flash NVM Standard Architecture Overview: NOR vs. NAND 195 |
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5.1.3.1 NOR-Flash 195 -- 5.1.3.2 NAND-Flash 197 -- 5.1.3.3 Summary 198 -- 5.2 Radiation-hard Flash Architecture Study 198 -- 5.2.1 Critical Features: Introduction of the Differential Cell Architecture 199 -- 5.2.2 Program -- Erase Circuit Analysis 202 -- 5.2.3 Read & Verify Circuit Analysis 207 -- 5.2.4 General Architecture Considerations and Internal Bit Structure 211 -- 5.2.5 Case Study: FP7 SkyFlash Project on Rad-hard Non-Volatile Memories 213 -- 5.3 Side-Circuits 218 -- 5.3.1 Charge Pump Analysis 219 -- 5.3.2 Charge Pump 221 -- 5.3.3 Pad-ring Requirements 222 -- 5.4 Conclusion 223 -- References 223 -- 6 Radiation Hardness of Foundry NVM Technologies 227 Evgeny Pikhay, Cristiano Calligaro and Yakov Roizin 6.1 Introduction 228 -- 6.2 Physical Phenomena in CMOS Devices Under Irradiation and Their Control 230 -- 6.3 Radiation Hardness of CMOS Logic Memories 234 -- 6.3.1 Single-Poly EEPROMs 234 -- 6.3.2 GOX Anti-Fuses 236 -- 6.3.3 Radioisotope-Powered Memory 238 -- 6.3.4 Silicon Nitride-Based Memories 239 -- 6.4 On the Chip Tools for TID Radiation Effects Control 247 -- 6.4.1 MOS Structures for Monitoring of Radiation-Induced Charges in Dielectrics 248 -- 6.4.2 FG Devices for Monitoring the TID 252 -- 6.4.2.1 Introduction 252 -- 6.4.2.2 C-Sensor operation principle 256 -- 6.4.2.3 Implementation of C-Sensor principle in CMOS platform 258 -- 6.4.2.4 Detecting different types of ionizing radiation using C-Sensor 259 -- 6.5 Conclusion 264 -- References 264 -- 7 Rad-hard Resistive Memories 269 Cristiano Calligaro 7.1 ReRAM Cell 269 -- 7.2 ReRAM Array 271 -- 7.3 ReRAM Architecture 277 -- 7.4 ReRAM Periphery 281 -- 7.5 Forming, Setting and Resetting a Resistive Memory 292 -- 7.6 Resistive OTPs (ROTPs): The ReRAM Pioneers 302 -- References 305 -- 8 Technologies for Rad-hard Resistive Memories 309 Christian Wenger 8.1 Non-Volatile Memory Technologies 309 -- 8.1.1 State-of-the-Art NVMs -- Flash Memory 311 -- 8.1.2 The Way-out Over Emerging Technologies 312 -- 8.1.3 ReRAM Technology 313 |
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8.2 Reliability Issues of 1T-1R-based HfO2 ReRAM Arrays 315 -- 8.2.1 Retention Results on Amorphous and Polycrystalline Arrays 322 -- 8.2.2 Set Evolution 322 -- 8.2.3 Reset Evolution 324 -- 8.2.4 Impact of Temperature on Conduction Mechanisms and Switching Parameters in HfO2-based 1T-1R ReRAM Devices 327 -- 8.3 CMOS Integration of Resistive Memory Cells 330 -- 8.4 Conclusions 337 -- References 338 -- 9 New Generation of NVMs Based on Graphene-related Nanomaterials 341 Paolo Bondavalli 9.1 Introduction 342 -- 9.2 Graphene-based Non-volatile Memories 343 -- 9.2.1 Graphene and Graphitic Layers 344 -- 9.2.2 Non-volatile Resistive Memories Based on GO and R-GO Oxide Layers 348 -- 9.3 Other Approaches to Achieve Non-volatile Memories Using Graphitic Layers 354 -- 9.3.1 Graphitic-based Non-volatile Memory Using a Transistor Configuration 355 -- 9.3.2 Non-volatile Flash-type Memories Based on Graphene/Multi-layered Graphene 357 -- 9.4 Conclusions 360 -- References 361 -- Index 369 -- About the Editors 373 |
| Summary |
Rad-hard Semiconductor Memories is intended for researchers and professionals interested in understanding how to design and make a preliminary evaluation of rad-hard semiconductor memories, making leverage on standard CMOS manufacturing processes available from different silicon foundries and using different technology nodes. In the first part of the book, a preliminary overview of the effects of radiation in space, with a specific focus on memories, will be conducted to enable the reader to understand why specific design solutions are adopted to mitigate hard and soft errors. The second part will be devoted to RHBD (Radiation Hardening by Design) techniques for semiconductor components with a specific focus on memories. The approach will follow a top-down scheme starting from RHBD at architectural level (how to build a rad-hard floor-plan), at circuit level (how to mitigate radiation effects by handling transistors in the proper way) and at layout level (how to shape a layout to mitigate radiation effects). After the description of the mitigation techniques, the book enters in the core of the topic covering SRAMs (synchronous, asynchronous, single port and dual port) and PROMs (based on AntiFuse OTP technologies), describing how to design a rad-hard flash memory and fostering RHBD toward emerging memories like ReRAM. The last part will be a leap into emerging memories at a very early stage, not yet ready for industrial use in silicon but candidates to become an option for the next wave of rad-hard components. Technical topics discussed in the book include: * Radiation effects on semiconductor components (TID, SEE) * Radiation Hardening by Design (RHBD) Techniques * Rad-hard SRAMs * Rad-hard PROMs * Rad-hard Flash NVMs * Rad-hard ReRAMs * Rad-hard emerging technologies |
| Bibliography |
Includes bibliographical references and index |
| Notes |
Online resource; title from digital title page (viewed on February 13, 2019) |
| Subject |
Semiconductors -- Effect of radiation on.
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Semiconductor storage devices.
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TECHNOLOGY & ENGINEERING -- Mechanical.
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Semiconductor storage devices
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Semiconductors -- Effect of radiation on
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| Form |
Electronic book
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| Author |
Calligaro, Cristiano, editor
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Gatti, Umberto, editor.
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| ISBN |
8770220190 |
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9788770220194 |
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1003339182 |
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9781003339182 |
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1000793060 |
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9781000793062 |
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