| Description |
1 online resource (xvii, 369 pages) : illustrations |
| Contents |
1. Introduction -- 2. Interconnection networks in network-on-chip -- 3. Architecture design of network-on-chip -- 4. Evaluation of network-on-chip architectures -- 5. Application mapping on network-on-chip -- 6. Low-power techniques for network-on-chip -- 7. Signal integrity and reliability of network-on-chip -- 8. Testing of network-on-chip architectures -- 9. Application-specific network-on-chip synthesis -- 10. Reconfigurable network-on-chip design -- 11. Three-dimensional integration of network-on-chip -- 12. Conclusions and future trends |
| Summary |
Addresses the Challenges Associated with System-on-Chip IntegrationNetwork-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design |
| Bibliography |
Includes bibliographical references |
| Notes |
English |
|
Online resource; title from PDF title page (EBSCO, viewed December 6, 2014) |
| Subject |
Networks on a chip.
|
|
TECHNOLOGY & ENGINEERING -- Mechanical.
|
|
Networks on a chip
|
| Form |
Electronic book
|
| Author |
Chattopadhyay, Santanu, author.
|
| ISBN |
9781466565272 |
|
1466565276 |
|
1322629250 |
|
9781322629254 |
|
1466565268 |
|
9781466565265 |
|
9781315216072 |
|
1315216078 |
|
9781351823272 |
|
1351823272 |
|
