Description |
1 online resource (xiii, 400 pages) : illustrations |
Series |
Lecture notes in computer science, 0302-9743 ; 4917 |
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LNCS sublibrary. SL 1, Theoretical computer science and general issues |
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Lecture notes in computer science ; 4917. 0302-9743
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LNCS sublibrary. SL 1, Theoretical computer science and general issues.
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Contents |
Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable -- ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache |
Summary |
This book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized in topical sections on Multithreaded and Multicore Processors, Reconfigurable - ASIP, Compiler Optimizations, Industrial Processors and Application Parallelization, Power-Aware Techniques, High-Performance Processors, Profiles: Collection and Analysis as well as Optimizing Memory Performance |
Analysis |
wiskunde |
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mathematics |
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datacommunicatie |
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data communication |
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ontwerp |
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design |
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computerwetenschappen |
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computer sciences |
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computernetwerken |
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computer networks |
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procesarchitectuur |
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process architecture |
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programmeertalen |
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programming languages |
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Information and Communication Technology (General) |
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Informatie- en communicatietechnologie (algemeen) |
Bibliography |
Includes bibliographical references and index |
Notes |
Print version record |
Subject |
Embedded computer systems -- Congresses
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Compilers (Computer programs) -- Congresses
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Computer architecture -- Congresses
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Informatique.
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Compilers (Computer programs)
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Computer architecture.
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Embedded computer systems.
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Genre/Form |
Conference papers and proceedings.
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Conference papers and proceedings.
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Actes de congrès.
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Form |
Electronic book
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Author |
Stenström, Per.
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LC no. |
2007942570 |
ISBN |
9783540775607 |
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3540775609 |
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9783540775591 |
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3540775595 |
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1281179825 |
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9781281179821 |
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9788354077565 |
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835407756X |
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