| Description |
1 online resource (xix, 132 pages) : illustrations |
| Series |
Synthesis lectures on digital circuits and systems, 1932-3174 ; #40 |
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Synthesis lectures on digital circuits and systems ; #40. 1932-3166
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| Contents |
Introduction to probabilistic computation models -- Nanoscale circuits and fluctuation problems -- Estimators and metrics -- MRF models of logic gates -- Neuromorphic models -- Noise-tolerance via error correcting -- Conclusion and future work |
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Preface -- Acknowledgments |
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1. Introduction to probabilistic computation models -- 1.1 Why do we need probabilistic models? -- 1.1.1 Noise -- 1.1.2 Ideal noise-free conditions -- 1.1.3 Noisy operation conditions -- 1.2 Probabilistic techniques and models -- 1.2.1 Popular probabilistic techniques -- 1.2.2 Probabilistic models based on local computation -- 1.2.3 Nearest neighbor methodologies -- 1.2.4 Bayesian belief propagation model -- 1.2.5 Markov random field model -- 1.2.6 Neuromorphic model -- 1.3 Hardware implementation -- 1.4 Concluding remarks |
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2. Nanoscale circuits and fluctuation problems -- 2.1 Nanostructures for logic circuits -- 2.1.1 Why nanostructures? -- 2.1.2 Nanostructure formation -- 2.1.3 Nanostructure network and switching function for circuitry -- 2.2 Fluctuation in nanodevices and their integrated circuits -- 2.3 Concluding remarks |
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3. Estimators and metrics -- 3.1 Why do we need new metrics? -- 3.1.1 Objective and subjective measures of belief -- 3.1.2 Logic operations and data structures -- 3.1.3 Operations with probabilities and data structure -- 3.1.4 Measures of uncertainty -- 3.2 Uncertainty representation and estimation -- 3.2.1 Variability and random variables -- 3.2.2 Parameter estimation -- 3.2.3 Probability metrics -- 3.2.4 Information-theoretic metrics -- 3.3 Measurement techniques -- 3.3.1 Kullback-Leibler divergence -- 3.3.2 Signal-to-noise ratio (SNR) -- 3.3.3 Bit error rate (BER) -- 3.4 Maximum-likelihood estimators -- 3.4.1 Formal notation -- 3.4.2 The simplest estimator -- 3.4.3 The best hardware estimator -- 3.5 Summary and discussion |
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4. MRF models of logic gates -- 4.1 Basic definitions -- 4.1.1 Graphical data structure -- 4.1.2 Formal notion of the MRF model -- 4.1.3 Logic function embedding -- 4.1.4 Implementation -- 4.2 MRF model of a binary inverter -- 4.2.1 Marginalization -- 4.2.2 Compatibility truth table -- 4.2.3 Feedback -- 4.3 MRF model implementation using cyclic BDDs -- 4.3.1 Measures for BDTs and BDDs -- 4.3.2 Cyclic BDTs and BDDs -- 4.4 Simulation -- 4.4.1 NOT gate CMOS implementation using a cyclic BDD -- 4.4.2 Comparison -- 4.5 Noise-tolerant two-bit adder -- 4.5.1 Shared BDDs -- 4.5.2 Shared cyclic BDD -- 4.6 Experimental study -- 4.6.1 Comparisons of two-bit adders -- 4.6.2 Area, power, and delay -- 4.6.3 Simulation results -- 4.7 Ternary inverter -- 4.7.1 Noise-tolerant ternary inverter -- 4.7.2 Ternary CMOS NOT and MIN-NOT gate -- 4.7.3 Comparison with conventional CMOS design -- 4.7.4 Area, power, and delay -- 4.8 Summary and discussion |
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5. Neuromorphic models -- 5.1 Hopfield network and Boltzmann machine -- 5.1.1 Threshold gate -- 5.1.2 Noise and measure of uncertainty -- 5.1.3 Network of threshold cells -- 5.1.4 Hopfield network -- 5.1.5 Boltzmann machine -- 5.1.6 Logic function embedding -- 5.2 Experiments -- 5.2.1 Metric -- 5.2.2 Updating -- 5.2.3 Networking Hopfield models of gates -- 5.2.4 Modeling and results -- 5.3 Multistate Hopfield model -- 5.4 Concluding remarks |
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6. Noise-tolerance via error correcting -- 6.1 Introduction -- 6.2 Background of error correcting techniques -- 6.3 Logic gate reliability -- 6.3.1 Multiplexer circuit reliabilitY -- 6.4 Noise modeling in BDDS -- 6.5 BDD model with error correction -- 6.5.1 BDDs for shortened codes -- 6.6 Reliability of error-correcting BDDs -- 6.7 Summary and discussion |
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7. Conclusion and future work -- Bibliography -- Authors' biographies |
| Summary |
Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed; as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation; specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers |
| Analysis |
nanotechnology |
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nanostructure |
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nanodevice |
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fluctuation |
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logic gate |
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noise-tolerance |
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fault-tolerance |
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Bayesian network |
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Markov random field |
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Hopfield model |
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Boltzmann machine |
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binary decision diagram |
| Notes |
Part of: Synthesis digital library of engineering and computer science |
| Bibliography |
Includes bibliographical references (pages 117-129) |
| Notes |
Online resource; title from PDF title page (Morgan & Claypool, viewed on February 17, 2013) |
| Subject |
Nanoelectromechanical systems -- Noise
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Fault-tolerant computing.
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Integrated circuits -- Fault tolerance.
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SCIENCE -- Physics -- Electricity.
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Fault-tolerant computing
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Integrated circuits -- Fault tolerance
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| Form |
Electronic book
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| Author |
Kasai, S., author.
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Tangim, G., author.
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Mohamed, T., author.
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Tran, A. H., author.
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Shmerko, Vlad P., author.
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| ISBN |
9781627050234 |
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162705023X |
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1627050221 |
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9781627050227 |
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9783031798559 |
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3031798554 |
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