Title Defect-oriented testing for nano-metric CMOS VLSI circuits / by Manoj Sachdev and José Pineda de Gyvez

Edition 2nd ed Published Dordrecht : Springer, ©2007

Click on the following:
Springer eBooks

Copies

Description 1 online resource (xxi, 328 pages) : illustrations Series Frontiers in electronic testing ; 34 Frontiers in electronic testing ; 34. Contents Cover -- Contents -- Dedication -- Preface -- Foreword -- Foreword for the First Edition -- Acknowledgements -- Chapter 1. Introduction -- 1. Evolution of CMOS Technology -- 2. The Test Complexity -- 3. Quality and Reliability Awareness -- 4. Building Quality and Reliability -- 5. Objectives of this Book -- 6. Book Organization -- Chapter 2. Functional and Parametric Defect Models -- 1. Brief Classification of Defects -- 1.1 Defect-Fault Relationship -- 2. Inductive Fault Analysis -- 2.1 IC Design and Layout Related Defect Sensitivity -- 2.2 Defect Sensitive Design -- 2.3 Basic Concepts of IFA -- 3. Parametric Defect and Fault Models -- 3.1 Threshold Voltage Mismatch (V<sub>t</sub>) Fault Modeling -- 3.2 Sources of Threshold Voltage Variability -- 3.3 Leakage Current due to V<sub>t</sub> Mismatch -- 3.4 Delay in Parallel-connected Networks -- 3.5 Delay Variation Model with V<sub>t</sub> for Parallel Transistor Networks -- 3.6 Spot Defect Statistics: Resistive Opens -- 4. Functional Defect Models -- 4.1 Critical Areas -- 4.2 Defect Statistics -- 4.3 Average Probability of Failure of Long Interconnects -- 4.4 Average Critical Area of N Conductors -- 5. Conclusions -- Chapter 3. Digital CMOS Fault Modeling -- 1. Objectives of Fault Modeling -- 2. Levels of Testing -- 3. Levels of Fault Modeling -- 3.1 Logic Level Fault Modeling -- 3.2 Transistor Level Fault Modeling -- 3.3 Layout Level Fault Modeling -- 3.4 Function Level Fault Modeling -- 3.5 Delay Fault Models -- 3.6 Leakage Fault Model -- 3.7 Temporary Faults -- 4. Conclusions -- Chapter 4. Defects in Logic Circuits and their Test Implications -- 1. Introduction -- 2. Stuck-at Faults and Manufacturing Defects -- 2.1 Study by Galiay, Crouzet and Vergniault -- 2.2 Study by Banerjee and Abraham -- 2.3 Study by Maly, Ferguson and Shen -- 2.4 Gate Oxide Shorts: Study by Hawkins and Soden -- 3. IFA Experiments on Standard Cells -- 4. I<sub>DDQ</sub> versus Voltage Testing -- 5. Defects in Sequential Circuits -- 5.1 Undetected Defects -- 5.2 Defect Detection Technique -- 5.3 I<sub>DDQ</sub> Testable Flip-flop -- 5.4 Defects and Scan Chains -- 6. Defect Classes and their Testing -- 7. Application of IFA in Nano-metric Technologies -- 8. Conclusions -- Chapter 5. Testing Defects and Parametric Variations in RAMs -- 1. Introduction -- 2. Traditional RAM Fault Models -- 2.1 Stuck-at Fault Model -- 2.2 Coupling Fault Model -- 2.3 Pattern Sensitivity Fault Model -- 3. Defect Based RAM Fault Model Development -- 3.1 Defect based SRAM Fault Models and Test Algorithms -- 3.2 Subsequent Defect-oriented SRAM Test Development -- 3.3 Defect based DRAM Fault Models and Test Algorithms -- 3.4 TCAM Fault Models and Test Algorithms -- 4. Address Decoder Defects -- 4.1 Early Work on Address Decoder Faults -- 4.2 Technological Differences -- 4.3 Failure and Analysis -- 4.4 Why Non-detection by March Tests? -- 4.5 Address Decoder Summary "Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts."--Jacket Notes New edition of: Defect oriented testing for CMOS analog and digital circuits, 1998 Bibliography Includes bibliographical references and index Notes Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. http://purl.oclc.org/DLF/benchrepro0212 MiAaHDL Print version record digitized 2010 HathiTrust Digital Library committed to preserve pda MiAaHDL Subject Metal oxide semiconductors, Complementary -- Testing. Metal oxide semiconductors, Complementary -- Defects Integrated circuits -- Very large scale integration -- Testing Integrated circuits -- Very large scale integration -- Defects TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Integrated. TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General. Integrated circuits -- Very large scale integration -- Testing. Integrated circuits -- Very large scale integration -- Defects. Metal oxide semiconductors, Complementary -- Testing. Metal oxide semiconductors, Complementary -- Defects. Ingénierie. Integrated circuits -- Very large scale integration -- Defects Integrated circuits -- Very large scale integration -- Testing Metal oxide semiconductors, Complementary -- Defects Metal oxide semiconductors, Complementary -- Testing Form Electronic book Author Pineda de Gyvez, José Sachdev, Manoj. Defect oriented testing for CMOS analog and digital circuits ISBN 9780387465470 0387465472 9780387465463 0387465464

  Permalink