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E-book

Title Design of cost-efficient interconnect processing units : Spidergon STNoC / Marcello Coppola [and others]
Published Boca Raton : CRC Press, ©2009

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Description 1 online resource (xxi, 265 pages) : illustrations
Series System-on-chip design and technologies
System-on-chip design and technologies.
Contents 1. Towards multicores : technology and software complexity -- 2. On-chip bus vs. network-on-chip -- 3. NoC topology -- 4. The Spidergon STNoC -- 5. SoC and NoC design methodology and tools -- 6. Conclusions and future work -- References -- Index
Summary This book presents streamlined design solutions specifically for NoC. To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques. A Balanced Analysis of NoC Architecture - As the first detailed description of the commercial Spidergon STNoC architecture, "Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC" examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: how the SoC and NoC technology works why developers designed it the way they did the system-level design methodology and tools used to configure the Spidergon STNoC architecture differences in cost structure between NoCs and system-level networks. From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors - all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns. It is an arsenal of practical learning tools at your disposal
Bibliography Includes bibliographical references (pages 235-261) and index
Notes Print version record
Subject ST Microelectronics.
SUBJECT ST Microelectronics fast
Subject Networks on a chip.
Microprocessors.
COMPUTERS -- Hardware -- Mainframes & Minicomputers.
Microprocessors
Networks on a chip
Mikroprocessorer.
Form Electronic book
Author Coppola, Marcello.
ISBN 9781420044720
1420044729
1420044710
9781420044713
1281863149
9781281863140
9781315219936
131521993X
9781351827133
1351827138