Title ESD protection device and circuit design for advanced CMOS technologies / Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev

Published [Dordrecht] : Springer, ©2008

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Description 1 online resource (xv, 227 pages) : illustrations Contents Cover -- Contents -- Dedication -- Preface -- Acknowledgments -- 1. Introduction -- 1. Nature Of ESD Phenomena -- 2. ESD Failures In Nanometric Technologies -- 2.1 Oxide Rupture (Breakdown) -- 2.2 Junction Filamentation and Spiking -- 2.3 Metalization and Polysilicon Burn-out -- 2.4 Charge Injection -- 3. Circuit Reliability: ESD Models -- 4. ESD Challenges For Advanced CMOS Technologies -- 4.1 Scaling of Metal Interconnects:Aluminum to Copper -- 4.2 Scaling of Inter-Level Dielectrics: SiO2 to Low-k Materials -- 5. ESD Design Window13; -- 6. Book Objective and Organization13; -- 7. Summary -- 2. ESD Models and Test Methods13; -- 1. Introduction13; -- 2. ESD Zapping Modes13; -- 3. HBM Model -- 4. MM Model -- 5. CDM Model -- 6. CBM Model -- 7. TLP Testing -- 8. Correlation Of ESD Test Methods -- 8.1 HBM and MM Correlation -- 8.2 HBM and TLP Correlation -- 8.3 CDM and vf-TLP Correlation -- 9. ESD Testers -- 10. Summary -- 3. ESD Devices For Input/Output Protection -- 1. Introduction13; -- 2. Non-Snapback Devices13; -- 2.1 P-N Junction Diode -- 2.2 Zener Diode -- 2.3 Polysilicon Diode -- 2.4 Stacked Diodes -- 3. Snapback Devices13; -- 3.1 MOSFET -- 3.2 Silicon Controlled Rectifier -- 3.3 Low Voltage Triggered SCR (LVTSCR) -- 3.4 Dual SCR -- 3.5 Gate and Substrate Triggering -- 4. Latch-up in ESD Protection Devices13; -- 4.1 Increasing the Holding Voltage -- 4.2 Increasing the Holding Current -- 5. ESD Devices Under Stress Conditions: Burn-In -- 6. Failure Criteria of ESD Devices13; -- 6.1 It2 Current Criterion -- 6.2 Leakage Current (Ioff) Criterion -- 6.3 Failure Temperature Criterion -- 7. Summary -- 4. Circuit Design Concepts For ESD Protection -- 1. Introduction13; -- 2. ESD Protection Networks13; -- 3. Distributed ESD Protection Networks -- 3.1 Distributed Boosted ESD Networks -- 4. Circuit Design Flow for ESD -- 4.1 Device Simulation and Calibration -- 4.2 Mixed-Mode ESD Simulation -- 4.3 Chip-Level ESD Simulation -- 4.4 Test Chip Development -- 4.5 ESD Measurements -- 5. Summary -- 5. ESD Power Clamps -- 1. Introduction13; -- 2. Static ESD Clamp -- 2.1 Diode-Based ESD Clamps -- 2.2 MOSFET-Based ESD Clamps -- 2.3 SCR-Based ESD Clamps -- 3. Transient Power Clamps -- 3.1 MOSFET and SCR-Based Transient Clamps -- 3.2 Three-Stage Transient Power ESD Clamp -- 3.3 SRAM-Based ESD Power Clamp -- 3.4 Thyristor-Based ESD Power Clamp -- 3.5 Flip-Flop-Based Transient Power Supply Clamp -- 4. Summary -- 6. ESD Protection Circuits For High-Speed I/OS -- 1. Introduction13; -- 2. Parasitic Capacitance Of ESD Protection Circuits -- 2.1 Reverse-Biased pn Junction Capacitance -- 2.2 Gate Capacitance of MOSFET -- 3. A 12-Bit 20 Ms/S Analog To Digital Converter [3] -- 4. a 14-bit 125ms/s analog to digital converter [5] -- 4.1 Volterra Series Analysis -- 4.2 ADC with ESD Protection -- 5. A 4gb/S Current Mode Logic Driver [9] -- 5.1 CML Driver Design -- 5.2 ESD Protection Methods -- 5.3 CML Driver with MOS-Based ESD Protection -- 5.4 CML Driver with SCR-Based ESD Protection -- 5.5 Discussion on Jitter-Capacitance Relation -- 6. Summary -- 7. ESD Protection for Smart Power Applications13; -- 1. Introduction13 Summary ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths Bibliography Includes bibliographical references and index Notes Print version record In Springer eBooks Subject Integrated circuits -- Protection Electronic apparatus and appliances -- Design and construction. Electronic apparatus and appliances -- Protection. Electric discharges. Metal oxide semiconductors, Complementary -- Design and construction Integrated circuits -- Design and construction. Metal oxide semiconductor field-effect transistors. Electric action of points. Electronics. Systems engineering. electronic engineering. systems engineering. TECHNOLOGY & ENGINEERING -- Electronics -- Solid State. TECHNOLOGY & ENGINEERING -- Electronics -- Semiconductors. Ingénierie. Electric action of points Electric discharges Electronic apparatus and appliances -- Design and construction Electronic apparatus and appliances -- Protection Integrated circuits -- Design and construction Integrated circuits -- Protection Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary -- Design and construction Form Electronic book Author Sarbishaei, Hossein. Sachdev, Manoj. ISBN 9781402083013 1402083017 9781402083006 1402083009 1281397946 9781281397942

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