| Description |
1 online resource (vi, 453 pages) : illustrations |
| Contents |
Cover -- Contents -- Preface -- Part I: PHYSICAL AND ELECTRICAL ISSUES -- 1 Communication-based Design for Network-on-Chip -- 2 Wires as Interconnects -- 3 Global Interconnect Analysis -- 4 Design Methodologies for On-Chip Inductive Interconnect -- 5 Clock Distribution for High-Performance Designs -- Part II: LOGICAL AND ARCHITECTURAL ISSUES -- 6 Error-Tolerant Interconnect Schemes -- 7 Power Reduction Coding for Buses -- 8 Bus Structures in Networks-on-Chip -- 9 From Buses to Networks -- 10 Arbitration and Routing Schemes for On-Chip Packet Networks -- Part III: DESIGN METHODOLOGY AND TOOLS -- 11 Self-Timed Approach for Noise Reduction in NoC -- 12 Formal Communication Modelling and Refinement -- 13 Network Centric System-Level Model for Multiprocessor System-on-Chip Simulation -- 14 Socket-based Design Techniques using Decoupled Interconnects -- Part IV: APPLICATION CASES -- 15 Interconnect and Memory Organization in SOCs for Advanced Set- Top Boxes and TV -- 16 A Brunch from the Coffee Table -- Case Study in NOC Platform Design -- Last Page |
| Bibliography |
Includes bibliographical references (pages 451-453) |
| Notes |
Print version record |
| Subject |
Interconnects (Integrated circuit technology)
|
|
Systems on a chip.
|
| Form |
Electronic book
|
| Author |
Nurmi, Jari.
|
| LC no. |
2004045945 |
| ISBN |
1402078358 (Cloth) |
|
1402078366 (electronic bk.) |
|
6610616825 |
|
9781402078354 (Cloth) |
|
9781402078361 (electronic bk.) |
|
9786610616824 |
|
