Description |
1 online resource (xix, 287 pages) : illustrations (some color) |
Contents |
pt. 1. Low-level design techniques -- pt. 2. System-level design techniques -- pt. 3. Future and emerging technologies |
Summary |
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures." escribes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; " pplies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; " ffers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings |
Analysis |
engineering |
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circuits |
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computertechnieken |
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computer techniques |
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computer software |
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Engineering (General) |
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Techniek (algemeen) |
Bibliography |
Includes bibliographical references and index |
Notes |
Print version record |
In |
Springer eBooks |
Subject |
Networks on a chip.
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Computer-aided design.
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Systems engineering.
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Computer-Aided Design
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systems engineering.
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computer-aided designs (visual works)
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computer-aided design (process)
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Ingénierie.
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Networks on a chip
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Form |
Electronic book
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Author |
Silvano, Cristina
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Lajolo, Marcello
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Palermo, Gianluca
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ISBN |
9781441969118 |
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144196911X |
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